1. Field of the Invention
The present invention relates to a multi-layer printed board with a plurality of layers. More particularly, the present invention relates to a multi-layer printed board including a plurality of signal layers each provided with a signal line, a through-hole electrically interconnecting the signal lines of the different signal layers, and a ground through-hole electrically interconnecting a plurality of ground layers or a plurality of power supply layers.
2. Description of the Background Art
In a printed board utilized for a communicating device, and the like, a high-density packaging and a high signaling rate are desired. In response, to achieve the high-density packaging, a printed board is generally formed of multiple layers, each with a signal line connected via a through-hole. To form the through-hole, a hole penetrating the printed board is firstly formed with a drill, or the like, such that the hole penetrates an enlarged electrode which is called land and is provided adjacent to the signal line. The hole is then plated inside or filled with a conductive material to interconnect the lands of the different signal layers to electrically interconnect signal interconnections. The land is provided for ensuring conduction in case of a positioning error in terms of positioning accuracy in forming a hole, and improving yield.
In a printed board with such a multi-layered configuration, however, as a signaling rate increases, impedance matching between a through-hole and a signal line deteriorates, disadvantageously resulting in degradation of a signal such as a distorted signal waveform.
The following are examples to improve impedance matching. In a multi-layer printed board described in Japanese Patent Laying-Open No. 11-54869, wherein a ground through-hole is provided adjacent to a through-hole connected to a micro strip line serving as a signal line, a diameter of the ground through-hole, and a distance from the through-hole connected to the micro strip line are adjusted to improve impedance matching. Also in a multi-layer printed board described in Japanese Patent Laying-Open No. 2002-111230, a ground/power supply layer placed immediately below a pad portion wider than a signal line is provided with a hollowed portion to reduce capacitive coupling to avoid impedance mismatching in the pad portion. In a multi-layer printed board described in Japanese Patent Laying-Open No. 2000-216510, the number of ground through-holes provided adjacent to a through-hole connected to a signal line is increased or decreased to improve impedance matching.
As a signaling rate increases, a signal frequency increases. In order to improve impedance matching to attain the ability to accommodate such a signal of high frequency, in the above mentioned multi-layer printed boards described in Japanese Patent Laying-Open Nos. 11-54869 and 2002-216510, a distance from the through-hole connected to the signal line must be decreased, and the number of the ground through-holes must be increased, respectively. However, a limit in manufacturing actually exists, which hinders an improvement exceeding a certain level.
As in the multi-layer printed board described in Japanese Patent Laying-Open No. 2002-111230, if a ground/power supply layer placed immediately below the pad portion is hollowed, impedance matching of a signal line placed immediately below a ground/power supply layer can deteriorate.